Many electrical circuits used in a wide variety of modern technologies require both digital and analog circuitry. In order to convert between analog signals and digital signals, and vice versa, many circuits include both analog-to-digital and digital-to-analog converters. One common method used to convert between analog signals and digital signals is known as pulse distribution, or density, modulation (PDM).
When converting a digital signal to an analog signals, PDM involves receiving a multi-bit parallel digital input signal and converting the digital input to a binary output signal consisting of a series of 1's and 0's. Each 1 or 0 is generated at a frequency set by a clock signal. In order to convert the PDM signal back into an analog signal, a low pass filter is often used which essentially “averages” the values of the series of 1's and 0's into an analog signal.
Typically, the ratio of the clock frequency to the pulse rate is very high, such as 1000 to 1. As a result, the useable bandwidth is usually several orders of magnitude lower than the clock frequency.
Accordingly, it is desirable to provide a method for generating a PDM signal in which the ratio of the system clock frequency to the fundamental frequency of the output PDM signal can be reduced. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.